1. Field of the Invention
The present invention generally relates to optical transmission systems, employing line terminating equipments, which are applicable to long-distance SDH networks, and more particularly to terrestrial ones employing forward error correcting (FEC) codes to improve signal quality such as a bit error rate (BER).
2. Prior Art
Synchronous Digital Hierarchy (SDH) network is constructed under concept of a multi-layer structure which consists of path layer, multiplex-section layer and regenerator-section layer. The path layer is established between path terminating equipments (PTEs); the multiplex-section layer is established between line-terminating multiplexers (LT-MUXs); and a regenerator-section is defined as an interval of distance between two neighboring repeaters. Digital communication between PTEs is completed in these SDH equipments as following sequence. Data included in a path payload are transferred from the PTE to the LT-MUX, at which a path is multiplexed together with other paths to constitute a Synchronous Transport Module frame (i.e., STM-frame) with a section overhead (SOH) processed. A resultant STM-frame is transmitted toward an opposite LT-MUX through multiple regenerator-sections each of which is connected by repeaters. The LT-MUX on a receiver side terminates the SOH of the STM-frame and demultiplexes it into paths, which are delivered to a destined PTE. According to the CCITT recommendations concerning SDH optic transmission, wherein CCITT is the former party of International Telecommunications Union-Telecommunication (ITU-T), the STM frame is depicted in a matrix-type arrangement of bytes and is mainly divided into two paths: SOH and payload. The SOH is divided into two sub-portions: regenerator-section overhead (RSOH) and multiplex-section overhead (MSOH). Each byte in the RSOH is processed at the regenerator-section layer, and that in the MSOH at the multiplex-section layer. A certain number of SOH bytes have been defined for particular usages, while other SOH bytes remain to be undefined, which will be required for further customized utilizations.
There are provided two kinds of repeaters: regenerator (REP) and linear-repeater (L-REP). The REP is an opto-electronic equipment using optical-electrical converters and has regenerating, retiming, and reshaping functions, so is complicated in configuration and is expensive compared to the L-REP. L-REPs containing Er-Doped Fiber Amplifiers (EDFAs) are expected to be deployed frequently in optical transmission systems in the near future because of their cost effectiveness and their flexibility in terms of an operational bit rate. In terrestrial systems, their deployment leads to a mixture of L-REPs and opto-electrical REPs, where expanding REP's span by replacing REP with L-REP realizes more cost effective systems. However, with fewer REPs, concatenation of more L-REPs causes optical noise accumulation and increases total dispersion of a fiber line between REPs, which degrades optical waveforms and results in a Bit Error Rate (BER) floor. For example, in 10 Gbit/s optical transmission system where 19 L-REPs are employed in total line distance is 1260 km, transmitting power increase as much as 4 dB improves BER only slightly from 10.sup.-9 to 10.sup.-11. This is reported by the paper of "Design and Operation of Transmission Lines containing Er-Doped Fiber Amplifiers" for IEEE GLOBECOM 1992, P. 1875, provided by K. Aoyama, Y. Yamabayashi and K. Hagimoto. Therefore, method improving BER independent to transmitting power is strongly demanded: correcting bit errors by using Forward Error Correcting (FEC) codes. So far, the technology is mainly applied to radio communication systems, such as satellite or mobile communication which has a limitation of the transmitting power. Efforts are now made to apply FEC coding techniques in optical transmission systems, particularly in submarine transoceanic ones. Some of the studies are described below.
In 1991, Moro and Candiani performed 200 km-565 Mbit/s (700 Mbit/s after coding) optical non-regenerative transmission. Result of their experiment is described by the paper entitled "565 Mbit/s Optical Transmission System for Repeaterless Sections up to 200 km", provided by P. Moro and D. Candiani for IEEE ICC, 1991, p.1217. BCH (167,151) code can perform error correcting function up to 2 bits in 167 bits, and a coding gain obtained was 2.5 dB, where `BCH` is an abbreviation for `Bose-Chaudhuri-Hocquenghem`. In 1992, Galba et al. demonstrated experiments using RS (255,239) code on a repeaterless transmission of 401 km at bit rate of 622 Mbit/s (710 Mbit/s after coding) as well as on a repeaterless transmission of 357 km at 2.4 Gbit/s (2.8 Gbit/s after coding), where `RS` is an abbreviation for `Reed-Solomon`. Results of the experiments are described in the paper entitled "410 km, 622 Mbit/s and 357 km, 2.488 Gbit/s IM/DD Repeaterless Transmission Experiments using Er-Doped Fiber Amplifiers and Error Correcting Code", provided by P. M. Galba, J. L. Pamart, R. Uhel, E. Leclerc, J. O. Prorud, F. X. Ollivier and S. Bordrieux for IEEE Photonics Technology Letters, Vol. 4, No. 10, 1992, p.1148. Despite their excellent correcting capability, these codes increase a line rate which may not be affordable in terrestrial high-speed systems: they are not consistent with a STM frame format based on the CCITT recommendation G. 707, 708, 709. These codes require a special transmission format, so all REPs employed in the system must be customized in order to cope with the special transmission format: conventional REPs cannot be applied to their FEC system.
Line rate increases can be avoided when check bits can be mapped into existing unused bytes in a signal form. Grover and Moore proposed an STS-1 path (52 Mbit/s) that is encoded in a (6208,6195) cyclic Hamming code. The proposal is described by the paper entitled "Design and Characterization of an Error-Correcting Code for the SONET STS-1 Tributary" provided by W. D. Grover and T. E. Moore for IEEE Transactions on Communications, Vol. 38, No. 4, p. 467. Thirteen check bits are mapped into Path Overhead (POH) auxiliary bytes in a SONET format. It requires no modification to physical interface or section termination circuits on the line. However, it is not straightforward to apply this proposal to paths other than STS-1. Concatenated Virtual Containers, such as VC-4-Xc (where X=1, 4, 16) will be introduced soon to convey ATM cells, where `ATM` is an abbreviation for `Asynchronous Transfer Mode`. Different codes have to be devised for those high-speed paths. Suzuki proposes an error correcting Hamming code for a concatenation path. The proposal is described by the paper of Japanese Patent Laid-Open No.6-29956, entitled "An Insertion Processing Method of Error Correcting Code in a SDH signal and an Optical Transmission Device", which is invented by Teruhiko Suzuki of Fujitsu Corporation Ltd. of Japan. Herein, a code-word is `VC-4-16c`. According to the proposal, check bytes generated are inserted into a staff area existing for idle bits, wherein the staff area is provided at location between POH and payload in the VC-4-16c. This situation is depicted in FIG. 21. However, the method cannot be accepted for error correction scheme on the path other than VC-4-16c. Different FEC codes are necessary for different path speeds, moreover the error correction scheme is not applicable to a VC-4 frame because it does not have the staff area. Both of the methods are designed under concept that FEC is performed at the path layer. In considering a fact that a transmission line is switched to a protection line at LT-MUX based on bit errors detected by embedded B2 bytes in the MSOH, error corrections at the path layer cannot relieve frequency of undesirable bit-losses caused by line switching.
Paxal et al. has proposed a Reed-Solomon (524,522) code. The proposal is described by the paper entitled "Error-Correction Coding for High-Speed Optical Transmission Systems Based on the Synchronous Digital Hierarchy", European Transactions on Telecommunications (ETT), Vol. 4, No. 6, pp.623 provided by V. Paxal, P. Jourdain and G. Karam. In their proposal, a STM-1 payload is divided into three parts and each fraction is coded in a 12-parallel manner. Check bytes created by a FEC circuit are inserted not only in MSOH but also in RSOH. Herein, a FEC code is independent of path size, however, a FEC circuit must be deployed in each REP, and all REP circuits would have to be customized. In addition, the FEC code requires different coding circuits for different STM-N (where N&gt;1) systems, while decoding process in each REP causes accumulation of significant end-to-end delay.
On the other hand, in a viewpoint of a processing circuit configuration, it is necessary to invent a special circuit configuration for the FEC code and its designing scheme is as follows:
A coding circuit of FEC codes in optical transmission systems is more complex than ordinary ones, because of large code-word size and because of its higher clock rate (e.g., 156 MHz). For the sake of low power consumption and cost effective implementations, the coding circuit could be realized on a C-MOS Field Programmable Gate Array (FPGA) circuit. However, at the higher clock rate (e.g., 156 MHz), it is impossible for FPGAs to process incoming data in a serial manner. Therefore, it is necessary to provide a special circuit configuration which enables parallel processing for the FEC codes.
An Example of a parallel processing circuit for cyclic codes is disclosed in the paper of Japanese Patent Laid-Open No. 52-86011, entitled "Error Correcting Device for Parallel Processing", which is invented by Nakamura of NEC Corporation Ltd. of Japan. In the paper, a (255,247) Hamming code for 4-parallel processing is described as an example. However, Nakamura's invention is not suitable for applications to FEC codes whose code-words are relatively large. The Nakamura's invention requires electric connections which generate data equivalent to a remainder of a specific polynomial division, expressed as follows: EQU r1(x.sup.64).sup.3 +r2(x.sup.64).sup.2 +r3(x.sup.64)+r4 mod (x.sup.8 +x.sup.4 +x.sup.3 +x.sup.2 +1) (1)
In the above expression, 64th powers of `x` is determined from a next equation (2), as follows: EQU 4.times.64=1 (mod 255) (2)
While in order to realize parallel processing of the FEC codes of large code-word size, division calculation, similar to (1), according to method of the Nakamura's invention, forces tremendous burdens to central processing unit (CPU). For example, a convenient mathematical program (e.g., Mathematica 2.0) takes more than six hours to obtain solution of 8-parallel processing of about 20000 code-word size. Therefore, it is necessary to provide a simple circuit configuration and its designing method in the parallel processing of large code-word.